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參數(shù)資料
| 型號： | 74ALVT16841DL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5V/3.3V ALVT 20-bit bus interface latch 3-State |
| 中文描述： | ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 96K |
| 代理商： | 74ALVT16841DL |
Philips Semiconductors
Product specification
74ALVT16841
2.5V/3.3V 20-bit bus interface latch (3-State)
1998 Feb 13
10
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
X
= V
OL
+ 0.3V at V
CC
V
Y
= V
OH
– 0.3V at V
CC
3.0V; V
M
= V
CC
/2 at V
CC
3.0V; V
X
= V
OL
+ 0.15V at V
CC
3.0V; V
Y
= V
OH
– 0.15V at V
CC
2.7V
2.7V
2.7V
t
w
(H)
t
PHL
t
PLH
nLE
nQx
SA00078
V
M
V
M
V
M
V
M
V
M
3.0V or V
CC
whichever
is less
0V
V
OH
V
OL
Waveform 1. Propagation Delay, Latch Enable Input to
Output, and Enable Pulse Width
nDx INPUT
V
M
t
PLH
t
PHL
nQx OUTPUT
V
M
V
M
V
M
SA00079
3.0V or V
CC
whichever
is less
0V
3.0V or V
CC
whichever
is less
0V
Waveform 2. Propagation Delay for Data to Outputs
NOTE
:
The shaded areas indicate when the input is
permitted to change for predictable output performance.
ééé
éééééééé
éééééééé
M
nDx
V
M
V
M
M
M
nLE
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
SA00080
M
0V
0V
3.0V or V
CC
whichever
is less
3.0V or V
CC
whichever
is less
Waveform 3. Data Setup and Hold Times
V
Y
V
M
V
M
V
M
nQx
t
PZH
t
PHZ
SH00007
nOE
0V
V
OH
0V
3.0V or V
CC
whichever
is less
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
V
X
V
OL
V
M
V
M
V
M
nQx
t
PZL
t
PLZ
SH00008
nOE
0V
0V
3.0V or V
CC
3.0V or V
CC
whichever
is less
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
相關PDF資料 |
PDF描述 |
|---|---|
| 74ALVT16899 | 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)(帶16位奇偶發(fā)生器/校驗器的2.5V/3.3V 18位鎖存收發(fā)器（三態(tài)）) |
| 74ALVT16899DGG | 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ALVT16952 | 2.5V/3.3V 16-bit registered transceiver (3-State)(2.5V/3.3V16位寄存收發(fā)器（三態(tài)）) |
| 74ALVT16952DGG | Hex Schmitt-Trigger Inverters 14-TSSOP -40 to 85 |
| 74ALVT16952DL | Hex Schmitt-Trigger Inverters 14-TSSOP -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVT16841DL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Latch |
| 74ALVT16899 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ALVT16899DGG | 制造商:NXP Semiconductors 功能描述: |
| 74ALVT16899DGG-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVT16952 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.5V/3.3V ALVT 16-bit registered transceiver 3-State |
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