參數(shù)資料
型號(hào)： 74ALVCH16501
廠商： NXP Semiconductors N.V.
英文描述： Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85
中文描述： 18位通用總線收發(fā)器，三態(tài)
文件頁(yè)數(shù)： 2/13頁(yè)
文件大?。?/td> 86K
代理商： 74ALVCH16501
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
2
1998 Sep 29
853–2091 20106
FEATURES
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
All inputs have bushold circuitry
Output drive capability 50
transmission lines @ 85
°
C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is High, the outputs are
active. When OE
AB
is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
. The output enables are complimentary (OE
AB
is active
High, and OE
BA
is active Low).
To ensure the high impedance state during power up or power
down, OE
BA
should be tied to V
CC
through a pullup resistor and
OE
AB
should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
= 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.8
3.0
ns
C
I/O
C
I
Input/output capacitance
8.0
pF
Input capacitance
4.0
pF
C
PD
Power dissipation capacitance per
latch
V
I
= GND to V
CC1
Outputs enabled
21
pF
Outputs disabled
3
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74ALVCH16501 DGG
DWG NUMBER
SOT364-1
相關(guān)PDF資料
PDF描述
74ALVCH6501 18-bit universal bus transceiver(18位通用總線收發(fā)器（三態(tài)）)
74ALVCH16540 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-PDIP -40 to 85
74ALVCH16540DGG Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-PDIP -40 to 85
74ALVCH16540DL Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SO -40 to 85
74ALVCH16543 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SO -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74ALVCH16501DG 功能描述:總線收發(fā)器 18BIT UNIV. BUS TRANXCVR 3-ST RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCH16501DGG 制造商:NXP Semiconductors 功能描述:
74ALVCH16501DGG,11 功能描述:總線收發(fā)器 18BIT UNIV. BUS RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74ALVCH16501DGG,112 制造商:NXP Semiconductors 功能描述:
74ALVCH16501DGG,118 制造商:NXP Semiconductors 功能描述:
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