參數(shù)資料
型號(hào): 74ALVCH162245
廠商: NXP Semiconductors N.V.
英文描述: 16-bit bus transceiver with direction pin and 30Ω termination resistor (3-State)(帶30Ω終端電阻器和定向引腳的16位總線收發(fā)器(三態(tài)))
中文描述: 16位方向針和30Ω端接電阻總線收發(fā)器(3態(tài))(帶30Ω終端電阻器和定向引腳的16位總線收發(fā)器(三態(tài)))
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 94K
代理商: 74ALVCH162245
Philips Semiconductors
Product specification
74ALVCH162245
16-bit bus transceiver with direction pin and
30
termination resistor (3-State)
2
1998 Jun 29
853-2085 19638
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
Bus hold on all data inputs
Integrated 30
termination resistor
DESCRIPTION
The 74ALVCH162245 is a 16-bit transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
The 74ALVCH162245 features two output enable (nOE) inputs for
easy cascading and two send/receive (nDIR) inputs for direction
control. nOE controls the outputs so that the buses are effectively
isolated. This device can be used as two 8-bit transceivers or one
16-bit transceiver.
The 74ALVCH162245 is designed with 30
series resistors in both
HIGH and LOW output states.
The 74ALVCH162245 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
GND
V
CC1
GND
GND
V
CC1
2A5
2A4
V
CC2
2A3
2A2
GND
2A1
2A0
1A7
1A6
GND
1A5
1A4
V
CC2
1A3
1A2
GND
1A1
1A0
1OE
21
22
23
24
25
26
27
28
GND
2DIR
2OE
2A7
2A6
GND
SW00198
1DIR
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Bn; Bn to An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.4
ns
C
I
C
I/O
Input capacitance
4.0
pF
Input/output capacitance
8.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
Outputs enabled
27
pF
Outputs disabled
4
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVCH162245 DL
ACH162245 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVCH162245 DGG
ACH162245 DGG
SOT362-1
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