參數(shù)資料
型號(hào): 74ALVC16244MTDX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
中文描述: ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: 6.10 MM, MO-153, TSSOP-48
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 84K
代理商: 74ALVC16244MTDX
Philips Semiconductors
Product specification
74ALVC16244/
74ALVCH16244
16-bit buffer/line driver (3-State)
2
1998 Jun 29
853-2082 19638
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74ALVCH16244 only)
Output drive capability 50
transmission lines @ 85
°
C
Current drive
±
24 mA at 3.0 V
DESCRIPTION
The 74ALVC16244(74ALVCH16244) is a 16-bit non-inverting
buffer/line driver with 3-State outputs. The device can be used as
four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-State
outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH on nOE causes the outputs to assume a high impedance
OFF-state.
The 74ALVCH16244 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
The 74ALVC16244 has 5V tolerant inputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
2Y0
3Y2
3Y3
V
CC
4Y0
4Y1
4A1
4A0
V
CC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
V
CC
1A3
1A2
GND
1A1
1A0
2OE
21
22
23
24
25
26
27
28
GND
4Y2
4Y3
4OE
3OE
4A3
4A2
GND
SW00194
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
V
CC
= 2.5V, CL = 30pF
V
CC
= 3.3V, CL = 50pF
1.9
1.9
ns
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
Outputs enabled
25
pF
Outputs disabled
4
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
in W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVC16244 DL
AC16244 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVC16244 DGG
AC16244 DGG
SOT362-1
48-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVCH16244 DL
ACH16244 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVCH16244 DGG
ACH16244 DGG
SOT362-1
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