參數(shù)資料
型號: 74ALVC162374T
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Triple 3-Input Positive-NAND Gates 14-TSSOP -40 to 85
中文描述: ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: 6.10 MM, MO-153, TSSOP-48
文件頁數(shù): 1/6頁
文件大小: 95K
代理商: 74ALVC162374T
2001 Fairchild Semiconductor Corporation
DS500688
www.fairchildsemi.com
October 2001
Revised October 2001
7
74ALVC162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26
Series Resistors in Outputs
General Description
The ALVC162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVC162374 is also designed with 26
series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74ALVC162374 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
I
1.65V–3.6V V
CC
supply operation
I
3.6V tolerant inputs and outputs
I
26
series resistors in outputs
I
t
PD
(CLK to O
n
)
3.9 ns max for 3.0V to 3.6V V
CC
5.3 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
I
Power-off high impedance inputs and outputs
I
Supports live insertion and withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter
X
to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
74ALVC162374T
Package Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
CP
n
I
0
I
15
O
0
O
15
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
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74ALVC16240 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
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