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參數(shù)資料
| 型號： | 74ALVC162334A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple 3-Input Positive-NAND Gates 14-SO -40 to 85 |
| 中文描述： | 16位倒使登記注冊的驅(qū)動程序和30ohm終端電阻三態(tài) |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 74ALVC162334A |
Philips Semiconductors
Product specification
74ALVC162334A
16-bit registered driver with inverted register enable
and 30
termination resistors (3-State)
2
2000 Mar 14
853-2197 23314
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Output drive capability 50
transmission lines @ 85
°
C
Current drive
±
24 mA at 3.0 V
Integrated 30
termination resistors
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162334A is an 16-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162334A is designed with 30
series resistors in both
HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
OE
Y
1
Y
2
Y
3
Y
4
Y
5
GND
V
CC
GND
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
GND
Y
12
Y
13
Y
14
Y
15
Y
16
GND
CP
GND
A
1
A
2
A
3
A
4
V
CC
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
LE
SH00198
V
CC
NC
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
V
CC
= 3.3 V, C
L
= 50 pF
2.9
3.5
3.3
ns
f
max
C
I
C
I/O
Maximum clock frequency
V
CC
= 3.3 V, C
L
= 50 pF
240
MHz
Input capacitance
4.0
pF
Input/Output capacitance
8.0
pF
C
PD
Power dissipation capacitance per buffer
V = GND to V
CC1
transparent mode
Output enabled
Output disabled
10
3
pF
Clocked mode
Output enabled
Output disabled
21
15
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALVC162334A4PA | 制造商:Integrated Device Technology Inc 功能描述: |
| 74ALVC162334ADG | 功能描述:總線收發(fā)器 16-BIT REG DRVR W/INV REG RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74ALVC162334ADGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit registered driver with inverted register enable and 30 W termination resistors (3-state) |
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| 74ALVC162334ADGG,112 | 制造商:NXP Semiconductors 功能描述: |
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