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參數(shù)資料
| 型號： | 74ALS74 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual D-type flip-flop with set and reset |
| 中文描述： | 雙D型觸發(fā)器設置和復位觸發(fā)器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 50K |
| 代理商： | 74ALS74 |
Philips Semiconductors
Product specification
74ALS74A
Dual D-type flip-flop with set and reset
2
1996 Jul 01
853–1278 01670
DESCRIPTION
The 74ALS74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock input.
When set and reset are inactive (High), data at the D input is
transferred to the Q and Q outputs on the Low-to-High transition of
the clock. Data must be stable just one setup time prior to the
Low-to-High transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
TYPE
TYPICAL f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS74A
150MHz
3.0mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
DRAWING
NUMBER
14-pin plastic DIP
74ALS74AN
SOT27-1
14-pin plastic SO
74ALS74AD
SOT108-1
14-pin plastic SSOP
Type II
74ALS74ADB
SOT337-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00045
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0, D1
Data inputs
1.0/2.0
20
μ
A/0.2mA
20
μ
A/0.2mA
40
μ
A/0.4mA
40
μ
A/0.4mA
CP0, CP1
Clock inputs (active rising edge)
1.0/2.0
SD0, SD1
Set inputs (active-Low)
2.0/4.0
RD0, RD1
Reset inputs (active-Low)
2.0/4.0
Q0, Q1, Q0, Q1
NOTE:
One (1.0) ALS unit load is defined as: 20
μ
A in the High state and 0.1mA in the Low state.
Data outputs
20/80
0.4mA/8mA
LOGIC SYMBOL
Q0 Q0 Q1 Q1
5
6
9
8
V
= Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
2
12
SF00046
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
相關PDF資料 |
PDF描述 |
|---|---|
| 74ALS74A | Dual D-type flip-flop with set and reset |
| 74ALS74AD | Dual D-type flip-flop with set and reset |
| 74ALS74AN | Dual D-type flip-flop with set and reset |
| 74ALS74 | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| 74ALS74 | Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS74A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual D-type flip-flop with set and reset |
| 74ALS74AD | 制造商:NXP Semiconductors 功能描述: |
| 74ALS74ADB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual D-type flip-flop with set and reset |
| 74ALS74AN | 制造商:Texas Instruments 功能描述: 制造商: 功能描述: 制造商:Fairchild Semiconductor Corporation 功能描述: 制造商:undefined 功能描述: |
| 74ALS760 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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