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參數(shù)資料
| 型號(hào)： | 74ALS373D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Latch/flip-flop |
| 中文描述： | ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | PLASTIC, SOL-20 |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大小： | 144K |
| 代理商： | 74ALS373D |
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Philips Semiconductors
Product specification
74ALS373/74ALS374
Latch/flip-flop
74ALS373
74ALS374
Octal transparent latch (3-State)
Octal D flip-flop (3-State)
2
1991 Feb 08
853–1243 01670
FEATURES
8-bit transparent latch – 74ALS373
8-bit positive edge triggered register – 74ALS374
3-State output buffers
Common 3-State output register
Independent register and 3-State buffer operation
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS373
6.0ns
14mA
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS374
50MHz
17mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
DRAWING
NUMBER
20-pin plastic DIP
74ALS373N, 74ALS374N
SOT146-1
20-pin plastic SOL
74ALS373D, 74ALS374D
SOT163-1
20-pin plastic SSOP
Type II
74ALS373DB, 74ALS374DB
SOT339-1
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7
Data inputs
1.0/1.0
20
μ
A/0.1mA
20
μ
A/0.1mA
20
μ
A/0.1mA
20
μ
A/0.1mA
E (74ALS373)
Enable input (active-High)
1.0/1.0
OE
Output enable inputs (active-Low)
1.0/1.0
CP (74ALS374)
Clock pulse input (active rising edge)
1.0/1.0
Q0 – Q7
One (1.0) ALS unit load is defined as: 20
μ
A in the High state and 0.1mA in the Low state.
3-State outputs
130/240
2.6mA/24mA
NOTE:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ALS373DB | Latch/flip-flop |
| 74ALS373N | Latch/flip-flop |
| 74ALS374 | Latch/flip-flop |
| 74ALS374D | Latch/flip-flop |
| 74ALS374N | Latch/flip-flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ALS373DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Latch/flip-flop |
| 74ALS373N | 制造商:NXP Semiconductors 功能描述: 制造商:North American Philips Discrete Products Div 功能描述:Latch, Single, 8 Bit, 20 Pin, Plastic, DIP 制造商:NXP Semiconductors 功能描述:Latch, Single, 8 Bit, 20 Pin, Plastic, DIP |
| 74ALS373NTI86 | 制造商:TI 功能描述:74ALS373N |
| 74ALS373WM | 制造商:Texas Instruments 功能描述: 制造商:National Semiconductor Corporation 功能描述:Electronic Component |
| 74ALS374 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Latch/flip-flop |
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