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參數(shù)資料
| 型號： | 74AHCT595 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit serial-in/serial or parallel-out shift register with output latches;3-state(帶輸出鎖存的8位串行輸入/串行或并行輸出移位寄存器；三態(tài)) |
| 中文描述： | 8位serial-in/serial或并行輸出的移位寄存器輸出鎖存器，3態(tài)（帶輸出鎖存的8位串行輸入/串行或并行輸出移位寄存器，三態(tài)） |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 103K |
| 代理商： | 74AHCT595 |
2000 Mar 15
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and from
40 to +125
°
C.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register.
DESCRIPTION
The 74AHC/AHCT595 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT595 is an 8-stage serial shift register
with a storage register and 3-state outputs. The shift
register has separate clocks.
Data is shifted on the positive-going transitions of the
SH
CP
input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D
S
) and a serial
standard output (Q
7
’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
All 9 outputs switching.
2.
3.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
SH
CP
to Q
7
’
ST
CP
to Q
n
MR to Q
7
’
input capacitance
maximum clock frequency
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
4.0
4.2
4.4
3.0
170
3.8
4.0
4.6
3.0
170
190
ns
ns
ns
pF
MHz
pF
C
I
f
max
C
PD
C
L
= 50 pF; f = 1 MHz; notes 1, 2 and 3 180
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