參數(shù)資料
型號: 74AHC30
廠商: NXP Semiconductors N.V.
英文描述: 8-input NAND gate(8輸入與非門)
中文描述: 8輸入與非門(8輸入與非門)
文件頁數(shù): 2/16頁
文件大?。?/td> 75K
代理商: 74AHC30
1999 Nov 30
2
Philips Semiconductors
Product specification
8-input NAND gate
74AHC30; 74AHCT30
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Output capability: standard
I
CC
category: SSI
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT30 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT30 provide the 8-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
A, B, C, D, E, F, G, H to Y
input capacitance
output capacitance
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
3.6
3.3
ns
C
I
C
O
C
PD
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
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