參數(shù)資料
型號： 74ACTQ74SJX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Dual D-Type Flip-Flop
中文描述： ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 5.30 MM, EIAJ TYPE2, SOP-14
文件頁數(shù)： 3/8頁
文件大?。?/td> 215K
代理商： 74ACTQ74SJX
3
www.fairchildsemi.com
7
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1:
Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild
does not recommend operation of FACT
circuits outside databook specifi-
cations.
DC Electrical Characteristics
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
PDIP package.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6:
Max number of data inputs (n) switching. (n
1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1 MHz.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
=
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
=
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or Sink Current
Junction Temperature (T
J
) PDIP
0.5V to
+
7.0V
20 mA
+
20 mA
0.5V to V
CC
+
0.5V
20 mA
+
20 mA
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
65
°
C to
+
150
°
C
±
300 mA
140
°
C
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
V/
t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
40
°
C to
+
85
°
C
125 mV/ns
Symbol
Parameter
V
CC
(V)
4.5
5.5
T
A
=
+
25
°
C
Typ
1.5
1.5
T
A
=
40
°
C to
+
85
°
C
Guaranteed Limits
2.0
2.0
Units
Conditions
V
IH
Minimum HIGH Level
Input Voltage
2.0
2.0
V
V
OUT
=
0.1V
or V
CC
0.1V
V
OUT
=
0.1V
or V
CC
0.1V
V
IL
Maximum LOW Level
Input Voltage
Minimum HIGH Level
4.5
5.5
4.5
1.5
1.5
4.49
0.8
0.8
4.4
0.8
0.8
4.4
V
V
OH
V
I
OUT
=
50
μ
A
Output Voltage
5.5
4.5
5.49
5.4
3.86
5.4
3.76
V
V
IN
=
V
or V
IH
I
OH
=
24 mA
I
OH
=
24 mA (Note 2)
5.5
4.86
4.76
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
V
I
OUT
=
50
μ
A
4.5
0.36
0.44
V
V
IN
=
V
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 4)(Note 5)
5.5
0.36
0.44
I
IN
I
OZ
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
5.5
±
0.1
±
1.0
μ
A
5.5
±
0.5
±
5.0
μ
A
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 2)
5.5
5.5
5.5
0.6
1.5
75
75
20.0
mA
mA
mA
μ
A
Maximum Quiescent Supply Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
5.5
2.0
5.0
1.1
1.5
V
V
OLV
5.0
0.6
1.2
V
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
V
IHD
V
ILD
5.0
1.9
2.2
V
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 4)(Note 6)
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