參數(shù)資料
型號： 74ACT715-R
廠商： Fairchild Semiconductor Corporation
英文描述： Programmable Video Sync Generator
中文描述： 可編程視頻同步發(fā)生器
文件頁數(shù)： 3/14頁
文件大?。?/td> 127K
代理商： 74ACT715-R
3
www.fairchildsemi.com
7
Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with-
respect-to the number of clock pulses per line and vertical
pulses are specified with-respect-to the number of lines per
frame.
REG0—STATUS REGISTER
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Bits 0–2
Bits 3–4
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse.
In Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse
active LOW. A value of 1 indicates an active HIGH pulse.
B5—
VCBLANK Polarity
B6—
VCSYNC Polarity
B7—
HBLHDR Polarity
B8—
HSYNVDR Polarity
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9—
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
B10—
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for
internal testing only.
B11—
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizon-
tal Sync and Blank pulses.
REG1—
Horizontal Front Porch
REG2—
Horizontal Sync Pulse End Time
REG3—
Horizontal Blanking Width
REG4—
Horizontal Interval Width
per Line
# of Clocks
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5—
Vertical Front Porch
REG6—
Vertical Sync Pulse End Time
REG7—
Vertical Blanking Width
REG8—
Vertical Interval Width
per Frame
# of Lines
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9—
Equalization Pulse Width End Time
REG10—
Serration Pulse Width End Time
REG11—
Equalization/Serration Pulse Vertical
Interval Start Time
REG12—
Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Inter-
rupt signal if used.
REG13— Vertical Interrupt Activate Time
REG14— Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15— Horizontal Cursor Position Start Time
REG16— Horizontal Cursor Position End Time
REG17— Vertical Cursor Position Start Time
REG18— Vertical Cursor Position End Time
B
2
B
1
B
0
VCBLANK VCSYNC HBLHDR HSYNVDR
0
0
0
CBLANK
CSYNC
(DEFAULT)
0
0
1
VBLANK
CSYNC
0
1
0
CBLANK
VSYNC
0
1
1
VBLANK
VSYNC
1
0
0
CBLANK
CSYNC
1
0
1
VBLANK
CSYNC
1
1
0
CBLANK
VSYNC
1
1
1
VBLANK
VSYNC
HGATE
VGATE
HBLANK
HGATE
HBLANK
CUSOR
HBLANK
CUSOR
HBLANK
VGATE
HSYNC
HSYNC
VINT
VINT
HSYNC
HSYNC
B
4
0
B
3
0
Mode of Operation
Interlaced Double Serration and
Equalization
(DEFAULT)
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration and Equalization
相關(guān)PDF資料
PDF描述
74ACT715-RSCX TV/Video Sync Circuit
74ACT715SCX TV/Video Sync Circuit
74ACT821MTC 10-Bit D-Type Flip-Flop
74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
74AC821SC 10-Bit D-Type Flip-Flop
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74ACT715RPC 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
74ACT715RSC 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
74ACT715-RSC 功能描述:IC GEN PROG VIDEO SYNC 20-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
74ACT715RSCX 功能描述:視頻 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
74ACT715SC 功能描述:多媒體雜項(xiàng) Prog Vid Sync Gen RoHS:否 制造商:Texas Instruments 類型: 通道數(shù)量: 轉(zhuǎn)換速率:540 Mbps 分辨率: 封裝 / 箱體:SOIC-16 封裝:Tube
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