參數(shù)資料
型號: 74ACT534SJ
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Selectable Polarity 16-TSSOP -40 to 85
中文描述: ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20
封裝: 5.30 MM, EIAJ TYPE2, SOP-20
文件頁數(shù): 2/7頁
文件大?。?/td> 74K
代理商: 74ACT534SJ
www.fairchildsemi.com
2
7
Functional Description
The ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Z
=
High Impedance
O
0
=
Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Output
CP
OE
D
O
L
H
L
L
L
H
L
L
X
O
0
Z
X
H
X
相關(guān)PDF資料
PDF描述
74ACT534SCX Octal D-Type Flip-Flop
74ACT534SJX +5V, +10V Precision Voltage References
74ACT563 Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40 to 85
74ACT563SC Two 1-Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40 to 85
74ACT563SCX 8-Bit D-Type Latch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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