參數(shù)資料
型號: 74ACT16657DLR
英文描述: Low-Power µP Reset Circuits in 3-Pin SC70/SOT23
中文描述: 雙8位總線收發(fā)器
文件頁數(shù): 1/8頁
文件大?。?/td> 58K
代理商: 74ACT16657DLR
1/8
April 2001
I
HIGH SPEED: t
PD
= 4.5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
μ
A(MAX.) at T
A
=25
°
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 10
IMPROVED LATCH-UP IMMUNITY
I
I
I
I
I
I
I
I
DESCRIPTION
The 74ACT10 is an advanced high-speed CMOS
TRIPLE 3-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
74ACT10
TRIPLE 3-INPUT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
SOP
TSSOP
74ACT10B
74ACT10M
74ACT10MTR
74ACT10TTR
TSSOP
DIP
SOP
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相關代理商/技術參數(shù)
參數(shù)描述
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