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參數資料
| 型號： | 74ACT11885 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit Magnitude Comparators(8位數值比較器) |
| 中文描述： | 8位幅度比較器（8位數值比較器） |
| 文件頁數： | 1/6頁 |
| 文件大小： | 53K |
| 代理商： | 74ACT11885 |
54ACT11885, 74ACT11885
8-BIT MAGNITUDE COMPARATORS
SCAS393 – JUNE 1988
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1988, Texas Instruments Incorporated
1
Latchable P Input ports with Power-Up
Clear
Choice of Logical or Arithmetic (2’s
Complement) Comparison
Data and PLE Inputs Utilize P-N-P Input
Transistors to Reduce DC Loading Effects
Approximately 35% Improvement in AC
Performance Over Schottky TTL while
Performing More Functions
Cascadable to n-Bits while Maintaining
High Performance
10% Less Power than STTL for an 8-Bit
Comparison
Inputs are TTL-Voltage Compatible
New flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
description
These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two
8-bit binary or two’s complement words. Two full decoded decisions about words P and Q are externally
available at two outputs. These devices are full expandable to any number of bits without external gates. The
P > Q and P < Q outputs of a stage handling less-significant bits may be connected to the P > Q and P < Q inputs
of the next stage handling more-significant bits to obtain comparisons of words of longer lengths. The cascading
paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two
alternative methods of cascading are shown in the typical application data.
The latch is transparent when P Latch Enable (PLE) is high; the P input port is latched when PLE is low. This
provides the designer with temporary storage for the P data word. The enable circuitry is implemented with
minimal delay times to enhance performance when cascaded for longer words. The PLE and P and Q data
inputs utilize p-n-p input transistors to reduce the low-level current input requirements to typically – 0.25 mA,
which minimizes dc loading effects.
The 54ACT11885 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
74ACT11885 is characterized for operation from – 40
°
C to 85
°
C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
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| 74ACT11B | TRIPLE 3-INPUT AND GATE |
| 74ACT11M | TRIPLE 3-INPUT AND GATE |
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| 74ACT139 | Dual 1-of-4 Decoder/Demultiplexer |
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| 74ACT11898DW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 74ACT125B | 功能描述:緩沖器和線路驅動器 Quad Bus Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT125M | 功能描述:緩沖器和線路驅動器 RO 511-74ACT125M-TR RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT125MTC | 功能描述:緩沖器和線路驅動器 Quad Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| 74ACT125MTC_Q | 功能描述:緩沖器和線路驅動器 Quad Buffer RoHS:否 制造商:Micrel 輸入線路數量:1 輸出線路數量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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