參數(shù)資料
型號: 74AC648SC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Single 8-Bit Inverting Bus Transceiver
中文描述: AC SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁數(shù): 1/7頁
文件大?。?/td> 73K
代理商: 74AC648SC
2000 Fairchild Semiconductor Corporation
DS010133
www.fairchildsemi.com
November 1988
Revised August 2000
7
74AC648
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figure 1, Figure 2, Figure 3, and
Figure 4.
Features
I
Independent registers for A and B buses
I
Multiplexed real-time and stored data transfers
I
3-STATE outputs
I
300 mil slim dual-in-line package
I
Outputs source/sink 24 mA
I
Inverted data to output
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
is a trademark of Fairchild Semiconductor Corporation.
Order Number
74AC648SC
74AC648SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A
0
A
7
Data Register A Inputs,
Data Register A 3-STATE Outputs
Data Register B Inputs,
Data Register B 3-STATE Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
B
0
B
7
CPAB, CPBA
SAB, SBA
DIR, G
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相關代理商/技術參數(shù)
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