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參數(shù)資料
| 型號： | 74AC299SJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Input Universal Shift/Storage Register |
| 中文描述： | AC SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 128K |
| 代理商： | 74AC299SJ |
www.fairchildsemi.com
2
7
Logic Symbols
IEEE/IEC
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
LOW-to-HIGH Transition
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S
0
and S
1
, as
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Inputs
Response
MR
S
1
X
H
L
H
L
S
0
X
H
H
L
L
CP
L
H
H
H
H
X
Asynchronous Reset; Q
0
–
Q
7
LOW
Parallel Load; I/O
n
o
Q
n
Shift Right; DS
0
o
Q
0
, Q
0
o
Q
1
, etc.
Shift Left, DS
7
o
Q
7
, Q
7
o
Q
6
, etc.
Hold
X
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