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參數(shù)資料
| 型號： | 74ABTL3205BB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 10-bit BTL transceiver with registers |
| 中文描述： | ABT SERIES, 10-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 105K |
| 代理商： | 74ABTL3205BB |
Philips Semiconductors
Product specification
74ABTL3205
10-bit BTL transceiver with registers
1995 Jun 16
8
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
BIASV
Bias pin DC current
V
CC
= 0 to 5.25V, Bn = 0 to 2.0 V
V
= 0 to 4.75 V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
4.5
5.5
V
I
BIASV
Bias pin DC current
Bias in DC current
1
mA
V
CC
= 4.5 to 5.5V, Bn = 0 to 2.0 V,
Bias V = 4.5 to 5.5V
10
μ
A
Bn
Bus voltage during prebias
B0 – B8 = 0V, Bias V = 5.0V
1.62
2.1
V
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C
= 5V
C
L
= 50pF, C
L
= 500
T
amb
= –40
°
C to +85
°
C
V
= 5V
±
10%
C
L
= 50pF, C
L
= 500
UNIT
MIN
TYP
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
Bn to An
Waveform 2
2.0
1.8
3.6
3.5
6.5
6.1
2.0
1.8
7.3
6.7
ns
y
t
PLH
t
PHL
Propagation delay,
BCLK1 to ACLK1
Waveform 2
2.0
1.8
3.8
3.6
6.5
6.1
2.0
1.8
7.3
6.7
ns
y
t
PLH
t
PHL
Propagation delay
BCLK1 to ACLKin
Waveform 2
2.0
1.8
3.7
3.7
6.5
6.1
2.0
1.8
7.3
6.7
ns
y
t
PLH
t
PHL
Propagation delay
BCLK2 to ACLK2
Waveform 2
2.0
1.8
3.7
3.9
6.5
6.1
2.0
1.8
7.3
6.7
ns
t
PLH
t
PHL
Propagation delay
BCLK2 to AFP
Waveform 2
2.0
1.8
3.8
3.9
6.5
6.1
2.0
1.8
7.3
6.7
ns
y
t
PZH
t
PLZ
Output Enable time
OEA1, OEA2, IEA to An
Waveform 1 2
Waveform 1, 2
2.0
1.8
3.8
2.5
6.5
6.1
2.0
1.8
7.3
6.7
ns
t
PHZ
t
PLZ
Output Disable time
OEA1, OEA2, IEA to An
Waveform 4 5
Waveform 4, 5
1.6
2.0
2.5
3.3
5.6
7.8
1.4
1.8
5.7
8.2
ns
t
TLH
t
THL
Output transition time, An Port
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
3.0
1.7
7.0
4.0
ns
t
SK
(p)
Pulse skew
2
|t
PHL
– t
PLH
|
MAX
Waveform 3
2.0
ns
NOTES:
1. |t
actual – t
actual| for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V
, loading, etc.).
2. t
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
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