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參數(shù)資料
| 型號(hào)： | 74ABT5074DB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronizing dual D-type flip-flop with metastable immune characteristics |
| 中文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP2-14 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 100K |
| 代理商： | 74ABT5074DB |
Philips Semiconductors Advanced BiCMOS Products
Product specification
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
December 15, 1994
5
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
T
amb
= +25
°
C
T
amb
= –40
°
C to +85
°
C
MIN
TYP
MAX
MIN
MAX
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
–0.9
–1.2
–1.2
V
V
OH
High-level output voltage
V
CC
= 4.5V; I
OH
= –15mA;
V
I
= V
IL
or V
IH
2.5
2.9
2.5
V
V
OL
Low-level output voltage
V
CC
= 4.5V; I
OL
= 20mA;
V
I
= V
IL
or V
IH
0.35
0.5
0.5
V
I
I
Input leakage current
V
CC
= 5.5V; V
I
= GND or 5.5V
±
0.01
±
1.0
±
1.0
μ
A
I
OFF
Power-off leakage current
V
CC
= 0.0V; V
O
or V
I
4.5V
±
5.0
±
100
±
100
μ
A
I
O
Output current
1
V
CC
= 5.5V; V
O
= 2.5V
–50
–75
–180
–50
–180
mA
I
CC
Quiescent supply current
V
CC
= 5.5V; V
I
= GND or V
CC
2
50
50
μ
A
I
CC
Additional supply current
per input pin
2
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
0.25
500
500
μ
A
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
°
C
V
CC
= +5.0V
TYP
T
amb
= –40 to +85
°
C
V
CC
= +5.0V
±
0.5V
MIN
UNIT
MIN
MAX
MAX
f
max
Maximum clock frequency
1
180
250
150
ns
t
PLH
t
PHL
Propagation delay
CPn to Qn or Qn
1
1.0
1.0
2.8
2.4
3.9
3.5
1.0
1.0
4.5
3.7
ns
t
PLH
t
PHL
Propagation delay
SDn, RDn
to Qn or Qn
2
1.0
1.0
3.5
3.1
4.6
4.2
1.0
1.0
5.5
4.7
ns
t
sk(o)
Output skew
1, 2
CPn to Qn to Qn
4
1.5
2.0
ns
NOTES:
1. | t
actual - t
actual | for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
°
C
V
CC
= +5.0V
T
amb
= –40 to +85
°
C
V
CC
= +5.0V
±
0.5V
UNIT
MIN
TYP
MIN
t
s
(H)
t
s
(L)
Setup time, High or Low
Dn to CPn
1
2.5
2.5
1.5
1.5
2.5
2.5
ns
t
h
(H)
t
h
(L)
Hold time, High or Low
Dn to CPn
1
0
0
–1.4
–1.4
0
0
ns
t
w
(H)
t
w
(L)
CPn pulse width,
high or low
1
1.5
2.4
0.6
1.8
1.5
2.9
ns
t
w
(L)
SDn or RDn pulse width, low
2
2.0
1.3
2.2
ns
t
rec
Recovery time
SDn or RDn to CPn
3
2.4
1.3
2.8
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 74ABT5074DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| 74ABT5074D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| 74ABT5074N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with metastable immune characteristics |
| 74ABT5074PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with metastable immune characteristics |
| 74ABT5074PW-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
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