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參數(shù)資料
| 型號(hào)： | 74ABT373CSMX |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Octal Transparent Latch with TRI-STATE Outputs |
| 中文描述： | 八路透明鎖存器與三態(tài)輸出 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 338K |
| 代理商： | 74ABT373CSMX |
Extended AC Electrical Characteristics
(SOIC package)
74ABT
74ABT
74ABT
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V to 5.5V
C
L
e
50 pF
8 Outputs Switching
(Note 4)
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V to 5.5V
C
L
e
250 pF
(Note 5)
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V to 5.5V
C
L
e
250 pF
8 Outputs Switching
(Note 6)
Symbol
Parameter
Units
Min
Max
Min
Max
Min
Max
t
PLH
t
PHL
Propagation Delay
D
n
to O
n
1.5
1.5
5.2
5.2
2.0
2.0
6.8
6.8
2.0
2.0
9.0
9.0
ns
t
PLH
t
PHL
Propagation Delay
LE to O
n
1.5
1.5
5.5
5.5
2.0
2.0
7.5
7.5
2.0
2.0
9.5
9.5
ns
t
PZH
t
PZL
Output Enable Time
1.5
1.5
6.2
6.2
2.0
2.0
8.0
8.0
2.0
2.0
10.5
10.5
ns
t
PHZ
t
PZL
Output Disable Time
1.0
1.0
5.5
5.5
(Note 7)
(Note 7)
ns
Note 4:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.).
Note 5:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in
the standard AC load. This specificaiton pertains to single output switching only.
Note 6:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 7:
The TRI-STATE delay times are dominated by the RC network (500
X
, 250 pF) on the output and has been excluded from the datasheet.
Skew
Symbol
Parameter
74ABT
74ABT
Units
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V–5.5V
C
L
e
50 pF
8 Outputs Switching
(Note 3)
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V–5.5V
C
L
e
250 pF
8 Outputs Switching
(Note 4)
Max
Max
t
OSHL
(Note 1)
Pin to Pin Skew
HL Transitions
1.0
1.5
ns
t
OSLH
(Note 1)
Pin to Pin Skew
LH Transitions
1.0
1.5
ns
t
PS
(Note 5)
Duty Cycle
LH–HL Skew
1.4
3.5
ns
t
OST
(Note 1)
Pin to Pin Skew
LH/HL Transitions
1.5
3.9
ns
t
PV
(Note 2)
Device to Device Skew
LH/HL Transitions
2.0
4.0
ns
Note 1:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW to HIGH and/or HIGH to LOW
(t
OST
). This specification is guaranteed but not tested.
Note 2:
Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not tested.
Note 3:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.).
Note 4:
This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load.
Note 5:
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the
outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
5
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