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參數(shù)資料
| 型號： | 74ABT273CSJ |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal D-Type Flip-Flop |
| 中文描述： | ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 74ABT273CSJ |
1999 Fairchild Semiconductor Corporation
DS011549
www.fairchildsemi.com
January 1993
Revised November 1999
7
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
I
Eight edge-triggered D-type flip-flops
I
Buffered common clock
I
Buffered, asynchronous Master Reset
I
See ABT377 for clock enable version
I
See ABT373 for transparent latch version
I
See ABT374 for 3-STATE version
I
Output sink capability of 64 mA, source capability of
32 mA
I
Guaranteed latchup protection
I
High impedance glitch free bus loading during entire
power up and power down cycle
I
Non-destructive hot insertion capability
I
Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
74ABT273CSC
74ABT273CSJ
74ABT273CMSA
74ABT273CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300
”
Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
D
0
–
D
7
MR
Data Inputs
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
Q
0
–
Q
7
Data Outputs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74ABT273CMSAX | Octal D-Type Flip-Flop |
| 74ABT273CMTCX | Ultra-Low-Power, Open-Drain, Single/Dual-Supply Comparators |
| 74ABT273CSCX | Ultra-Low-Power, Open-Drain, Single/Dual-Supply Comparators |
| 74ABT273CSJX | Octal D-Type Flip-Flop |
| 74ABT373 | Octal Transparent Latch with 3-STATE Outputs(八D型鎖存器（三態(tài)輸出）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74ABT273CSJ_Q | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ABT273CSJX | 功能描述:觸發(fā)器 Oct D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74ABT273D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| 74ABT273DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| 74ABT273D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
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