參數(shù)資料
型號: 74ABT16244ADGG,118
廠商: NXP Semiconductors
文件頁數(shù): 12/12頁
文件大小: 0K
描述: IC BUFF DVR TRI-ST 16BIT 48TSSOP
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 2,000
系列: 74ABT
邏輯類型: 緩沖器/線路驅(qū)動器,非反相
元件數(shù): 4
每個元件的位元數(shù): 4
輸出電流高,低: 32mA,64mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應商設備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 568-8767-2
74ABT16244ADGG,118-ND
935203300118
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX02 Rev. 1.6.0
9
74LCX02
Lo
w
V
olta
g
e
Quad
2-Input
NOR
Gate
with
5V
T
olerant
Inputs
Physical Dimensions (Continued)
Figure 5. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specications do not expand the terms of Fairchild’s worldwide terms and conditions,
specically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00
°TOP & BOTTOM
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
相關PDF資料
PDF描述
1776149-6 TERM BLOCK HEADER 6POS STR 7.5MM
284516-5 TERM BLOCK HEADER 5POS STR 3.5MM
1546208-5 TERM BLOCK PLUG 5POS R/A 5MM
1-796695-1 TERM BLOCK HEADER 11POS R/A .137
1-796694-1 TERM BLOCK HEADER 11PS VERT .137
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