參數(shù)資料
型號: 74244
廠商: Fairchild Semiconductor Corporation
英文描述: Octal 3-STATE Buffer/Line Driver/Line Receiver
中文描述: 八路三態(tài)緩沖器/線路驅動器/線接收器
文件頁數(shù): 1/6頁
文件大?。?/td> 65K
代理商: 74244
2000 Fairchild Semiconductor Corporation
DS008442
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS244
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description
These buffers/line drivers are designed to improve both the
performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock driv-
ers, and bus-oriented transmitters/receivers. Featuring 400
mV of hysteresis at each low current PNP data line input,
they provide improved noise rejection and high fanout out-
puts and can be used to drive terminated lines down to
133
.
Features
I
3-STATE outputs drive bus lines directly
I
PNP inputs reduce DC loading on bus lines
I
Hysteresis at data inputs improves noise margins
I
Typical I
OL
(sink current)
I
Typical I
OH
(source current)
I
Typical propagation delay times
Inverting
10.5 ns
Noninverting
12 ns
I
Typical enable/disable time
I
Typical power dissipation (enabled)
Inverting
130 mW
Noninverting
135 mW
24 mA
15 mA
18 ns
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
L
=
LOW Logic Level
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
Z
=
High Impedance
Order Number
DM74LS244WM
DM74LS244SJ
DM74LS244N
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
G
L
L
H
A
L
H
X
Y
L
H
Z
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