參數(shù)資料
型號: 7403
廠商: Fairchild Semiconductor Corporation
英文描述: Quad 2-Input NAND Gates with Open-Collector Outputs
中文描述: 四2輸入與非門與集電極開路輸出
文件頁數(shù): 13/28頁
文件大小: 163K
代理商: 7403
September 1993
13
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
With FIFO full; SI held HIGH in anticipation of empty location
Notes to Fig.7
1.
2.
3.
4.
5.
FIFO is initially full, shift-in is held HIGH
SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
handbook, full pagewidth
SI INPUT
MGA660
3
4
DIR OUTPUT
VM
(1)
2
bubble - up
delay
VM
(1)
5
SO INPUT
tPLH
VM
(1)
1
tW
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
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74HC7404 5-Bit x 64-word FIFO register; 3-state
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