- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360463 > 7403 (意法半導體) BASIC SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | 7403 |
| 廠商： | 意法半導體 |
| 英文描述： | BASIC SIGNAL PROCESSOR |
| 中文描述： | 基本信號處理器 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 163K |
| 代理商： | 7403 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁
September 1993
24
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Expanded format
Figure 20 shows two cascaded FIFOs
providing a capacity of 128 words x
4 bits. Figure 21 shows the signals on
the nodes of both FIFOs after the
application of a SI pulse, when both
FIFOs are initially empty. After a
ripple through delay, data arrives at
the output of FIFO
A
. Due to SO
A
being HIGH, a DOR
A
pulse is
generated. The requirements of SI
B
and D
nB
are satisfied by the DOR
A
pulse width and the timing between
the rising edge of DOR
A
and Q
nA
.
After a second ripple through delay,
data arrives at the output of FIFO
B
.
Figure 22 shows the signals on the
nodes of both FIFOs after the
application of aSO
B
pulse, when both
FIFOs are initially full. After a
bubble-up delay a DIR
B
pulse is
generated, which acts as aSO
A
pulse
for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input
of FIFO
B
. The requirements of the
SO
A
pulse for FIFO
A
is satisfied by
the pulse width of DOR
B
. After a
second bubble-up delay an empty
space arrives at D
nA
, at which time
DIR
A
goes HIGH. Figure 23 shows
the waveforms at all external nodes of
both FIFOs during a complete shift-in
and shift-out sequence.
Note to
Fig.20
The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between
FIFO
A
and FIFO
B
. Figure 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
shifted empty again.
Fig.20 Cascading for increased word capacity; 128 words x 4 bits.
MGA679
DIR
OE
SI
MR
DnA
4
DIR
SI
DOR
SO
DATA INPUT
A
A
4
SOA
DORA
QnA
7403
FIFO A
DIR
OE
SI
MR
DnB
B
B
4
SOB
QnB
DORB
7403
FIFO B
DATA OUTPUT
OE
MR
相關PDF資料 |
PDF描述 |
|---|---|
| 7403 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| 74HC7404 | 5-Bit x 64-word FIFO register; 3-state |
| 74HC7404D | 5-Bit x 64-word FIFO register; 3-state |
| 74HC7404N | 5-Bit x 64-word FIFO register; 3-state |
| 74HCT7404 | Dual 4-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7403 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 7403 | 制造商:Thomas & Betts 功能描述:GROMMET GLAND |
| 74030 | 制造商:MYRRA 功能描述:TRANSFORMER EE25 30W 制造商:Myrra 功能描述:TRANSFORMER, EE25, 30W 制造商:MYRRA 功能描述:TRANSFORMER, EE25, 30W; Primary Voltages:65V to 130V; Secondary Voltages:5V, 2 x 12V; Current Rating:3A; Power Rating:30W; Plug Type:-; SVHC:No SVHC (19-Dec-2012); AC Power:30W; External Depth:27mm; External Length / Height:21mm; ;RoHS Compliant: Yes |
| 74030 | 制造商:MYRRA 功能描述:TRANSFORMER EE25 30W |
| 74030 | 制造商:Myrra 功能描述:TRANSFORMER, 5V/12V, 30W, EE25 |
發(fā)布緊急采購，3分鐘左右您將得到回復。