參數(shù)資料
型號(hào)： 7403
廠商： NXP Semiconductors N.V.
英文描述： 4-Bit x 64-word FIFO register; 3-state
中文描述： 4位× 64字的FIFO寄存器，三態(tài)
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 163K
代理商： 7403
September 1993
26
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Notes to Fig.22
1.
2.
3.
FIFO
A
and FIFO
B
initially full, SI
B
held HIGH in anticipation of shifting in new data as an empty location bubbles-up
Unload one word from FIFO
B
; SO pulse applied, results in DOR pulse
DIR
B
and SO
A
pulse HIGH; (bubble-up delay after SO
B
LOW) data is loaded into FIFO
B
as a result of the DIR pulse,
data is shifted out of FIFO
A
DOR
A
and SI
B
go LOW; flag indicates the output stage of FIFO
A
is busy, shift-in to FIFO
B
is complete
DOR
A
and SI
B
go HIGH; flag indicates valid data is again available at FIFO
A
output stage, SI
B
is held HIGH, awaiting
bubble-up of empty location
DIR
A
goes HIGH; (bubble-up delay after SO
A
LOW) an empty location is present at input stage of FIFO
A
.
4.
5.
6.
Fig.22 FIFO to FIFO communication; output timing under full condition.
handbook, full pagewidth
VM
(1)
DORB
SOB
VM
(1)
MGA667
4
5
6
DIR A
QnA
nB
D
SOA
DIRB
DORASIB
VM
(1)
2
bubble - up
delay
VM
(1)
VM
(1)
bubble - up
delay
1
3
相關(guān)PDF資料
PDF描述
7403 BASIC SIGNAL PROCESSOR
7403 Quad 2-Input NAND Gates with Open-Collector Outputs
74HC7404 5-Bit x 64-word FIFO register; 3-state
74HC7404D 5-Bit x 64-word FIFO register; 3-state
74HC7404N 5-Bit x 64-word FIFO register; 3-state
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