參數(shù)資料
型號(hào): 73S1217F-68IMR/F/P
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 85/93頁(yè)
文件大小: 0K
描述: IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
73S12xxF Software User Guide
UG_12xxF_016
86
Rev. 1.50
4.5.1
EMV LEVEL I Certification Tests
The EMV compliant test suite follows the Payment System Environment specification. There are several
test labs, listed on the www.emvco.com website, qualified to perform these tests.
Currently, there are two available Protocol test suites that can be used to qualify for EMV Level I
compliance. Passing either of these suites will qualify as EMV Level I compliance. The Pseudo-CCID
code links to the two TSC libraries LAPI and HAPI which comply with both tests. However, since each
lab has its own test scripts and the test scripts differ according to the lab’s setup, the application layer
must be written and adapted specifically for each test lab’s requirements. The following subsections
describe the loopback tests that are to be written either on the host side or added to the TSC Pseudo-
CCID firmware.
4.5.1.1 EMV Test Mode
An EMV test (or session) is defined as a Command/Response pair that runs from the Activation of the
card to the Deactivation of the card. A Block Transfer may or may not occur during the session
depending on the card’s ATR response.
The host may set up the EMV PSE test environment via the USB CCID Card Control command (Escape
command). The first parameter byte (B1) of the Escape command must specifically indicate whether a
test mode is invoked and if so, it should be invoked using the MCI, VISA I or VISA II test environment.
Review the Escape command section for details about this test mode.
Following a successful Escape command, the host should start the test by sending the PowerOn
command (ScardConnect). Depending on the status of the ATR (good or bad), the host should send an
empty Block Transfer command without the APDU command (command length = 0). For example: 6F
00 00 00 00… CRC.
The test loopback will be handled by the firmware and upon completion of each test, the firmware will
respond to the host with the status, indicating whether the test session completed with a successful
return code or not. An unsuccessful return code may or may not indicate that the test failed. The test
result (test passed or test failed) is determined only by the card side.
Figure 11 depicts the minimal coding required on the host side to invoke the EMV PSE test environment.
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73S1217F-68M/F/PE 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
73S1217F-68MR/F/PE 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
73S1217F-EB 功能描述:開(kāi)發(fā)板和工具包 - 8051 73S1217F Eval Brd (Usb Cable, Doc. Cd) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1217F-EB-Lite 功能描述:開(kāi)發(fā)板和工具包 - 8051 73S1217F EVB Lite w/Plug & Play/Usb RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評(píng)估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: