參數(shù)資料
型號: 73S1210F-EB-LITE
廠商: Maxim Integrated Products
文件頁數(shù): 42/126頁
文件大小: 0K
描述: BOARD EVAL 73S1210F LITE DOC/CBL
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
73S1210F Data Sheet
DS_1210F_001
22
Rev. 1.4
All ports on the chip are bi-directional. Each consists of a Latch (SFR ‘USR70’), an output driver, and an
input buffer, therefore the MPU can output or read data through any of these ports if they are not used for
alternate purposes.
1.6
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 73S12xxF Software User’s Guide.
1.7
Peripheral Descriptions
1.7.1
Oscillator and Clock Generation
The 73S1210F has one oscillator circuit for the main CPU clock. The main oscillator circuit is designed to
operate with various crystal or external clock frequencies. An internal divider working in conjunction with a
PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended
frequency for proper operation of specific peripheral blocks such as the specific timers, ISO 7816 UART
and interfaces, Step-up converter, and keypad. The clock generation and control circuits are shown in
VCO
Phase
Freq
DET
CPU CLOCK
DIVIDER
6 bits
MCLK
96MHz
1.5-48MHz
MPU CLOCK - CPCLK
SMART CARD LOGIC
BLOCK CLOCK
SCCLK
SCLK
CLOCK
Prescaler 6bits
SC/SCE
CLOCK
Prescaler 6bits
SEL
ETU CLOCK
DIVIDER
12 bits
CPUCKDiv
See SC Clock descriptions for more accurate diagram
ETUCLK
MCount(2:0)
KEYCLK
I2CCLK
1kHz
400kHz
DIVIDE
by 120
DIVIDER
/93760
HIGH
XTAL
OSC
X12IN
X12OUT
M DIVIDER
/(2*N + 4)
HCLK
HOSCen
12.00MHz
d
iv
2
ICLK
SCCKenb
SELSC
DIVIDE
by 96
CLK1M
1MHz
7.386MHz
3.6923MHz
I2C_2x
800kHz
d
iv
2
SCECLK
d
iv
2
d
iv
2
Figure 3: Clock Generation and Control Circuits
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