參數(shù)資料
型號(hào)： 73S1210F-44MR/F/PC
廠商： Maxim Integrated
文件頁數(shù)： 111/126頁
文件大?。?/td> 0K
描述： IC SOC SMART CARD READER 44QFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
85
Card Status/Control Register (CRDCtl): 0xFE05
0x00
This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This
register must be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-
up/down enable before setting CDETEN. The card detect logic is functional even without smart card logic
clock. When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.
Table 77: The CRDCtl Register
MSB
LSB
DEBOUN
CDETEN
–
DETPOL
PUENB
PDEN
CARDIN
Bit
Symbol
Function
CRDCtl.7
DEBOUN
Debounce - When set = 1, this will enable hardware debounce of
the card detect pin. The debounce function shall wait for 64ms of
stable card detect assertion before setting the CARDIN bit. This
counter/timer uses the keypad clock as a source of 1kHz signal.
De-assertion of the CARDIN bit is immediate upon de-assertion
of the card detect pin(s).
CRDCtl.6
CDETEN
Card Detect Enable - When set = 1, activates card detection
input. Default upon power-on reset is 0.
CRDCtl.5
–
CRDCtl.4
–
CRDCtl.3
DETPOL
Detect Polarity - When set = 1, the DETCARD pin shall interpret
a logic 1 as card present.
CRDCtl.2
PUENB
Enable pull-up current on DETCARD pin (active low).
CRDCtl.1
PDEN
Enable pull-down current on DETCARD pin.
CRDCtl.0
CARDIN
Card Inserted - (Read only). 1 = card inserted, 0 = card not
inserted. A change in the value of this bit is a “card event.” A
read of this bit indicates whether smart card is inserted or not
inserted in conjunction with the DETPOL setting.
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73S1210F-68M/F/PB 制造商:Maxim Integrated Products 功能描述:- Trays
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