參數(shù)資料
型號： 73S1210F-44M/F/PC
廠商： Maxim Integrated
文件頁數(shù)： 123/126頁
文件大?。?/td> 0K
描述： IC SOC SMART CARD READER 44QFN
標(biāo)準(zhǔn)包裝： 260
系列： *
73S1210F Data Sheet
DS_1210F_001
96
Rev. 1.4
FD Control Register (FDReg): 0xFE13
0x11
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The
maximum supported F/D ratio is 4096.
Table 90: The FDReg Register
MSB
LSB
FVAL.3
FVAL.2
FVAL.1
FVAL.0
DVAL.3
DVAL.2
DVAL.1
DVAL.0
Table 91: The FDReg Bit Functions
Bit
Symbol
Function
FDReg.7
FVAL.3
Refer to the Table 93 above. This value is converted per the table to
set the divide ratio used to generate the baud rate (ETU). Default,
also used for ATR, is 0001 (Fi = 372). This value is used by the
selected interface.
FDReg.6
FVAL.2
FDReg.5
FVAL.1
FDReg.4
FVAL.0
FDReg.3
DVAL.3
Refer to Table 93 above. This value is used to set the divide ratio
used to generate the smart card CLK. Default, also used for ATR, is
0001 (Di = 1).
FDReg.2
DVAL.2
FDReg.1
DVAL.1
FDReg.0
DVAL.0
Table 92: Divider Ratios Provided by the ETU Counter
FI (code)
0000
0001
0010
0011
0100
0101
0110
0111
Fi (ratio)
372
558
744
1116
1488
1860
⊕
FCLK max
4
5
6
8
12
16
20
⊕
FI(code)
1000
1001
1010
1011
1100
1101
1110
1111
Fi(ratio)
512
⊕
512
768
1024
1536
2048
⊕
2048
⊕
FCLK max
5
⊕
5
7.5
10
15
20
⊕
20
⊕
DI(code)
0000
0001
0010
0011
0100
0101
0110
0111
Di(ratio)
1
⊕
1
2
4
8
16
32
⊕
DI(code)
1000
1001
1010
1011
1100
1101
1110
1111
Di(ratio)
12
20
16
⊕
16
⊕
16
⊕
16
⊕
16
⊕
16
⊕
Note: values marked with
⊕ are not included in the ISO definition and arbitrary values have been
assigned.
The values given below are used by the ETU divider to create the ETU clock. The entries that are not
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are
within 1% of the target value.
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