
73M2901/5V
Advanced Single
Chip Modem
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3
μ
s. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
3
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSBit shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
CTS
/
RTS
flow control;
DCR
,
DSR
and
DTR
. In
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN NAME
VPA
VNA
VPD
32-PIN 44-PIN
15
21
6, 25,
29
5, 22,
26
TYPE
I
I
I
DESCRIPTION
Positive analog voltage (+ Analog Supply)
Negative analog voltage. (Analog Ground)
Positive digital voltage (+ Digital Supply)
16
22
2,12,
27, 33
11, 24,
44, 28
VND
I
Negative digital voltage. (Digital Ground)
ANALOG INTERFACE PIN DESCRIPTION
PIN NAME
RXA
TXAN
TXAP
HBDEN
32-PIN 44-PIN
20
16
17
14
TYPE
I
O
O
I
DESCRIPTION
Receive analog data
Transmit Analog -
Transmit Analog +
2w/4w hybrid driver enable pin
0 = Driver configured for 50k
or greater load (Tie to VND)
1 = Driver configured for driving line-coupling transformer (Tie to
VPD)
Analog Band Gap voltage reference pin (0.1
μ
F to VNA)
Analog reference voltage pin (0.1
μ
F to VNA)
21
17
18
15
VBG
VREF
EXTERNAL INTERRUPTS PIN DESCRIPTIONS
19
18
20
19
O
O
PIN NAME
RING
ASRCH
DTR
32-PIN 44-PIN
2
1
32
TYPE
I
I
I
DESCRIPTION
External interrupt – Line interface ring detection circuitry input
External interrupt – Autobaud detection, connected to TXD
External interrupt – DTE DTR signal input
39
38
37