參數(shù)資料
型號: 73M1903C-IM/F
廠商: Maxim Integrated Products
文件頁數(shù): 7/48頁
文件大?。?/td> 0K
描述: IC MODEM AFE MULTIREGIONAL 32QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 490
通道數(shù): 2
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN(5x5)
包裝: 管件
DS_1903C_033
73M1903C Data Sheet
Rev. 5.0
15
4
GPIO Registers
The 73M1903C provides 8 user definable I/O pins. Each pin is programmed separately as either an input
or an output by a bit in a direction register. If the bit in the direction register is set high, the corresponding
pin is an input whose value is read from the GPIO data register. If it is low, the pin will be treated as an
output whose value is set by the GPIO data register.
To avoid unwanted current contention and consumption in the system from the GPIO port before the
GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input
structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO
direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
Register02 (DATA): Address 02h
Reset State FFh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIO(7:0)
(0X02[7:0])
Bits in this register will be asserted on the GPIO(7:0) pins if the
corresponding direction register bit is a 0. Reading this address will return data reflecting
the values of pins GPIO(7:0).
Register03 (DIR): Address 03h
Reset State FFh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
DIR(7:0)
(0X03[7:0])
This register is used to designate the GPIO pins as either inputs or
outputs. If the register bit is reset to 0, the corresponding GPIO pin is programmed as an
output. If the register bit is set to a 1, the corresponding pin will be configured as an input.
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