參數(shù)資料
型號(hào)： 73K224BL
廠(chǎng)商： TDK Corporation
英文描述： V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid(V.22bis/V.22/V.21/Bell 212A/103單片Modem w/ 集成混合電路)
中文描述： V.22bis/V.22/V.21/Bell 212A/103單芯片調(diào)制解調(diào)器瓦特/集成混合（V.22bis/V.22/V.21/Bell 212A/103單片調(diào)制解調(diào)器瓦特/集成混合電路）
文件頁(yè)數(shù)： 5/33頁(yè)
文件大小： 270K
代理商： 73K224BL
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
5
PIN DESCRIPTION
POWER
NAME
PIN
TYPE
DESCRIPTION
GND
1
I
System ground
VDD
16
I
Power supply input, 5 V ±10% (73K224BL). Bypass with 0.1
and 22 μF capacitors to GND.
VREF
31
O
An internally generated reference voltage. Bypass with
0.1 μF capacitor to ground.
ISET
28
I
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 M
resistor. ISET should be bypassed to GND with a
0.1 μF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
13
I
ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on
CS
.
AD0-AD7
5-12
I/O
ADDRESS/DATA
multiplexed lines carry information to and from the internal
registers.
BUS:
These
bi-directional
tri-state
CS
23
I
CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if
CS
(latched) is not active. The state of
CS
is latched on the
falling edge of ALE.
CLK
2
O
OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
INT
20
O
INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt.
INT
will stay low until the processor
reads the detect register or does a full reset.
RD
15
I
READ: A low requests a read of the 73K224BL internal
registers. Data can not be output unless both
RD
and the
latched
CS
are active or low.
RESET
30
I
RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
相關(guān)PDF資料
PDF描述
73K224L V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
73K224L-28IH V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
73K224L-IGT V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
73K224L-IH V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
73K224L-IP V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
73K224BL-IGT 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Single-Chip Modem w/ Integrated Hybrid
73K224BL-IH 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Single-Chip Modem w/ Integrated Hybrid
73K224BL-IH/F 功能描述:電信集成電路 Modem Data Pump With Hybrid Relay Driver RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
73K224BL-IHR/F 功能描述:電信集成電路 Modem Data Pump With Hybrid Relay Driver RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
73K224L 制造商:TERIDIAN 制造商全稱(chēng):TERIDIAN 功能描述:Single-Chip Modem
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*