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參數(shù)資料
| 型號： | 72821L15TF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 1K X 9 BI-DIRECTIONAL FIFO, 10 ns, PQFP64 |
| 封裝： | SLIM, TQFP-64 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 72821L15TF8 |
7
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
LDA
LDA WENA1
WENA1
WCLKA
OPERATION ON FIFO A
LDB
LDB WENB1
WENB1
WCLKB
OPERATION ON FIFO B
00
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
No Operation
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
Figure 2. Writing to Offset Registers for FIFOs A and B
A read and write should not be performed simultaneously to the offset
registers.
OUTPUTS:
Full Flag (
FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA
(
FFB) will go LOW after 256 writes to the IDT72801's FIFO A (B); 512 writes
totheIDT72811'sFIFOA(B);1,024writestotheIDT72821'sFIFOA(B);2,048
writes to the IDT72831's FIFO A (B); 4,096 writes to the IDT72841's FIFO A
(B); or 8,192 writes to the IDT72851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionofthe
Write Clock WCLKA (WCLKB).
Empty Flag (
EFA, EFB) —EFA(EFB)willgoLOW,inhibitingfurtherread
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA(EFB)is synchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72801 - DUAL 256 x 9
72811 - DUAL 512 x 9
7
80
(MSB)
1
00
87
0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72831 - DUAL 2,048 x 9
72851 - DUAL 8,192 x 9
7
80
(MSB)
0
2
(MSB)
0
3
80
(MSB)
0
2
(MSB)
0
3
80
8
0
80
(MSB)
1
0
3034 drw 04
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
72841 - DUAL 4,096 x 9
7
80
(MSB)
0
4
80
(MSB)
0
4
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
72821 - DUAL 1,024 x 9
7
80
(MSB)
0
1
80
(MSB)
0
1
NOTE:
1. For the purposes of this table,
WENA1 and WENB1 = VIH.
2. The same selection sequence applies to reading from the registers.
RENA1 and
RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-
HIGH transition of RCLKA (RCLKB).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 72821L15TFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 1KX9X2 64TQFP - Tape and Reel |
| 72821L25PF | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72821L25PF8 | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72821L25PFI | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72821L25PFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 1KX9X2 64TQFP - Tape and Reel |
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