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參數資料
| 型號： | 7203L12PDG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 9 OTHER FIFO, 12 ns, PDIP28 |
| 封裝： | GREEN, PLASTIC, DIP-28 |
| 文件頁數： | 14/14頁 |
| 文件大?。?/td> | 114K |
| 代理商： | 7203L12PDG |
9
COMMERCIAL,INDUSTRIALANDMILITARY
TEMPERATURERANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
OCTOBER 22, 2008
Figure 9. Half-Full Flag Timing
Figure 10. Expansion Out
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by
eachsystem(i.e.
FFismonitoredonthedevicewhereWisused;EFismonitored
onthedevicewhere
Risused).ForadditionalinformationontheIDT7203/7204/
7205/7206/7207, refer to Tech Note 8: Operating FIFOs on Full and Empty
Boundary Conditions and Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7203/7204/7205/7206/7207/7208 may be used when the
applicationrequirementsarefor2,048/4,096/8,192/16,384/32,768/65,536words
or less. These FIFOs are in a Single Device Configuration when the Expansion
In (
XI) control input is grounded (see Figure 12).
Depth Expansion
These FIFOs can easily be adapted to applications when the require-
ments are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words.
Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/
7206/7207/7208s. Any depth can be attained by adding additional IDT7203/
7204/7205/7206/7207/7208s. ThesedevicesoperateintheDepthExpansion
mode when the following conditions are met:
1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(
FL)control
input.
2. All other devices must have
FLin the HIGH state.
3. The Expansion Out (
XO)pinofeachdevicemustbetiedtotheExpansion
In (
XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (
FF)andEmpty
Flag (
EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite
FFor EF). See Figure 14.
5. The Retransmit (
RT) function and Half-Full Flag (HF) are not available in
the Depth Expansion Mode.
For additional information on the IDT7203/7204/7205/7206/7207, refer to
Tech Note 9: Cascading FIFOs or FIFO Modules.
W
R
HF
HALF-FULL OR LESS
MORE THAN HALF-FULL
HALF-FULL OR LESS
tRHF
tWHF
2661 drw11
W
R
XO
WRITE TO
LAST PHYSICAL
LOCATION
tXOL
tXOH
READ FROM
LAST PHYSICAL
LOCATION
2661 drw12
tXOH
tXOL
W
R
XI
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
tXI
tXIR
2661 drw13
tXIS
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 7203L12TP | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7203L12TPG | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7203L15J | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7203L15J8 | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 7203L15JGI | 制造商:Integrated Device Technology Inc 功能描述:FIFO - Bulk |
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