參數(shù)資料
型號(hào): 71V433S11PFI
廠商: Integrated Device Technology, Inc.
英文描述: 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs
中文描述: 32K的× 32 3.3同步SRAM的流量通過(guò)輸出
文件頁(yè)數(shù): 8/19頁(yè)
文件大?。?/td> 261K
代理商: 71V433S11PFI
8
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(V
DD
= 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
Figure 3. Lumped Capacitive Load, Typical Derating
Figure 2. High-Impedence Test Load
(for t
OHZ
, t
CHZ
, t
OLZ
, and t
DC1)
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range
(1)
(V
HD
= V
DDQ
0.2V
,
V
LD
= 0.2V)
351
+3.3V
317
5pF*
3729 drw 04
DATA OUT
1
2
3
4
20 30 50
100
200
t
CD
(Typical, ns)
Capacitance (pF)
80
5
6
3729 drw 05
NOTE:
1. The
LBO
pin will be internally pulled to V
DD
if it is not actively driven in the application and the ZZ pin will be internally pulled to V
SS
if not actively driven.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|
LI
|
Input Leakage Current
V
DD
= Max., V
IN
=
0V to V
DD
___
5
μA
|
LI
|
ZZ &
LBO
Input Leakage Current
(1)
V
DD
= Max., V
IN
=
0V to V
DD
___
30
μA
|
LO
|
Output Leakage Current
CE
> V
IH
or
OE
> V
IH
, V
OUT
= 0V to V
DD
, V
DD
= Max.
___
5
μA
V
OL
Output Low Voltage
I
OL
= 5mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= –5mA, V
DD
= Min.
2.4
___
V
3729 tbl 12
NOTES:
1. All values are maximumguaranteed values.
2. At f = f
MAX,
inputs are cycling at the maximumfrequency of read cycles of 1/t
CYC
while
ADSC
= LOW; f=0 means no input lines are changing.
IDT71V433S11
IDT71V433S12
Symbol
Parameter
Test Conditions
Coml.
Ind.
Coml.
Ind.
Unit
I
DD
Operating Core Power
Supply Current
Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
220
220
210
210
mA
I
SB
Standby Core Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
45
45
40
40
mA
I
SB1
Full Standby Core Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2)
15
15
15
15
mA
I
ZZ
Full Sleep Mode Core
Power Supply Current
ZZ > V
HD
, V
DD
= Max.
15
15
15
15
mA
3729 tbl 13
*Including scope and jig capacitance.
AC Test Conditions
AC Test Loads
Figure 1. AC Test Load
50
DATA
OUT
Z
0
= 50
3729 drw 03
V
DDQ
/2
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3.0V
2ns
1.5V
1.5V
See Figures 1 and 2
3729 tbl 14
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