參數(shù)資料
型號(hào): 71V424VL15YGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 512K X 8 STANDARD SRAM, 15 ns, PDSO36
封裝: 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-36
文件頁(yè)數(shù): 2/9頁(yè)
文件大?。?/td> 523K
代理商: 71V424VL15YGI
6.42
IDT71V424S/YS/VS, IDT71V424L/YL/VL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit) Commercial and Industrial Temperature Ranges
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
NC
NC
A9
A8
A7
WE
I/03
I/02
V
SS
V
DD
I/01
I/00
CS
A2
A3
A4
A1
A0
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A18
A15
OE
I/07
I/06
V
SS
V
DD
I/05
I/04
A14
A13
A12
A11
A10
NC
NC
NC
NC
SO44-2
3622 drw 11
NC
NC
A16
A17
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
V
DD
V
SS
I/O 2
I/O 3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
A18
A17
A16
A15
OE
I/O 7
I/O 6
V
SS
V
DD
I/O 5
I/O 4
A14
A13
A12
A11
A10
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SO36-1
19
NC
3622 drw 02
SOJ
Top View
Truth Table
(1,2)
Capacitance
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Pin Configuration
TSOP
Top View
A
0
– A
18
Address Inputs
Input
CS
Chip Select
Input
WE
Write Enable
Input
OE
Output Enable
Input
I/O
0
- I/O
7
Data Input/Output
I/O
V
DD
3.3V Power
Power
V
SS
Ground
Gnd
3622 tbl 02
Pin Description
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
3622 tbl 03
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected - Standby (I
SB
)
V
HC
(3)
X
X
High-Z
Deselected - Standby (I
SB1
)
3622 tbl 01
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
DD
-0.2V.
3. Other inputs
V
HC
or
V
LC
.
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