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參數(shù)資料
| 型號(hào)： | 70824L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 25 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 70824L25PF |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
13
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port(1,6)
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port(1,6,7)
NOTES:
1. R/
W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/
W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of
CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the
CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6.
OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required tDW. If
OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP. For the
CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8.
CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
CE, LB, UB
ADDR
tAW
tWR
tDW
I/OIN
tWC
tWP
tDH
R/
W
tAS
I/OOUT
tWHZ
tBE
tACS
OE
tOHZ
tOW
3099 drw 15
(5)
(2)
(3)
Data Out
(4)
Valid Data In
(8)
tWR
CE,
LB, UB
tAW
tDW
I/OIN
ADDR
tWC
R/
W
tDH
tAS
3099 drw 16
Valid Data
(5)
tBP
(2)
tCW
(2)
(3)
(8)
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