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參數(shù)資料
| 型號： | 7005 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | ACT7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem |
| 中文描述： | ACT7005/7006單一封裝解決方案雙收發(fā)器，協(xié)議，子系統(tǒng) |
| 文件頁數(shù)： | 21/29頁 |
| 文件大小： | 452K |
| 代理商： | 7005 |
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Aeroflex Circuit Technology
SCD7005 REV B 8/2/01
Plainview NY (516) 694-6700
21
24
ENABLE
Enable. When held low, enables Bit Decode, Next Status, and
Status Update program lines.
62
INT #l
Good Block (RT) / VALID TRANSFER (BC)
63
INT #2
VALID Transmit (RT) / INVALID TRANSFER (BC)
33
LTFAIL
Loop Test Fail. This line goes low if any error in the terminals
own transmitted waveform is detected or if any parity error in the
hardwired RT address is detected.
3
MEREQ
Message Error Request. To set the Message Error bit in the
Status Word, this signal must go low within 650 nsec of INCMD
going low and remain valid for the DURATION of INCMD.
57
MODEREST
Mode Reset. This line pulses low for 500 ns on completion of
the servicing of a valid Reset Remote Terminal Mode
Command.
28
M16/8
Programs Interface for 8 Bit or 16 Bit Data Buses.
16/8 = LOW (0) 8 BIT MODE
16/8 = HIGH (1) 16 BIT MODE
55
NBGT
New Bus Grant. Pulses low whenever a new command is
accepted.
26
NEXT STATUS
Next Status. When held low, causes TF or SSF to appear in very
next Status Word after fault occurrence (except for Transmit
Status or Transmit Last Command).
58
PASS
Pass. Interrupt indicates that the protocol self-test has
completed with no faults.
88
RD
Read Strobe. Must GO LOW together with DS to perform a
READ OPERATION. Note: WT STROBE MUST BE HIGH.
61
RETRY
Retry Interrupt
31
RESET
System MASTER Reset. When low resets all registers and
INPUT/OUTPUT FIFO buffers. Minimum Low Time for reset 0.5
μsec.
17
RTADPAR
RT Address Parity. This must be hardwired by the user to give
odd parity.
22
RTAD0
RT Address Lines. These should be hardwired
by the user. RTAD4 is the most significant bit.
21
RTAD1
20
RTAD2
19
RTAD3
18
RTAD4
Pin #
Signal Name
Signal Description
Table 11 – Pin Number Description (continued)
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