參數(shù)資料
型號: 6A259
廠商: Allegro MicroSystems, Inc.
英文描述: 8-BIT ADDRESSABLE DMOS POWER DRIVER
中文描述: 8位可尋址的DMOS功率驅(qū)動器
文件頁數(shù): 5/10頁
文件大小: 205K
代理商: 6A259
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
www.allegromicro.com
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
Four modes of operation are selectable by controlling the
CLEAR and ENABLE inputs as shown above.
In the addressable-latch mode, data at the DATA input is
written into the addressed transparent latch. The addressed
output inverts the data input with all other outputs remaining
in their previous states.
In the memory mode, all outputs remain in their previous
states and are unaffected by the DATA or address (S
n
) inputs.
To prevent entering erroneus data in the latches, ENABLE
should be held HIGH while the address lines are changing.
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
In the clear mode, all outputs are OFF and are unaffected
by the DATA or address (S
N
) inputs.
Given the appropriate inputs, when DATA is LOW for a
given address, the output is OFF; when DATA is HIGH, the
output is ON and can sink current.
DATA INPUT REQUIREMENTS
Data Active Time Before Enable
(Data Set-Up Time), t
su(D)
..............................................
20 ns
Data Active Time After Enable
(Data Hold Time), t
h(D)
...................................................
20 ns
Data Pulse Width, t
w(D)
.......................................................
40 ns
Input Logic High, V
IH
................................................
0.85V
DD
Input Logic Low, V
IL
.................................................
0.15V
DD
50%
Dwg. WP-037
ENABLE
DATA
50%
w(D)
t
su(D)
t
h(D)
t
PHL
t
PLH
t
50%
ADDRESSED
OUTPUT
Dwg. WP-036
10%
90%
f
t
r
t
ENABLE
DATA
OUTPUT SWITCHING TIME
LOGIC SYMBOL
G8
Z9
Z10
9,0D
10,0R
OUT
0
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
S
1
S
2
DATA
CLEAR
ENABLE
Dwg. FP-046-2
0
2
S
0
8M 0/7
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
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