參數(shù)資料
型號: 69190-405
廠商: Impala Linear Corporation
英文描述: 50/100M SOT-23 CMOS RF LDO REGULATORS
中文描述: 50/100M的SOT - 23 CMOS射頻LDO穩(wěn)壓器
文件頁數(shù): 9/16頁
文件大小: 424K
代理商: 69190-405
50/100mA SOT-23 CMOS RF LDO Regulators
Impala Linear Corporation
9
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
4
5
1
2
3
Connect C
IN
between V
IN
of the ILC7080/81 and the
“GROUND PLANE”.
Keep the ground side of C
OUT
and C
NOISE
connected to
the “LOCAL GROUND” and not directly to the
“GROUND PLANE”.
On multilayer boards use component side copper for
grounding around the ILC7080/81 and connect back to a
“GROUND PLANE” using vias.
If using a DC-DC converter in your design, use a star
grounding system with separate traces for the power
ground and the control signals. The star should radiate
from where the power supply enters the PCB.
Place all RF LDO related components; ILC7080/81,
input capacitor C
IN
, noise bypass capacitor C
NOISE
and
output capacitor C
OUT
as close together as possible.
Keep the output capacitor C
OUT
as close to the
ILC7080/81 as possible with very short traces to the
V
OUT
and GND pins.
The traces for the related components; ILC7080/81,
input capacitor C
IN
, noise bypass capacitor C
NOISE
and
output capacitor C
OUT
can be run with minimum trace
widths close to the LDO.
Maintain a separate “LOCAL GROUND” remote from
the “GROUND PLANE” to ensure a quiet ground near
the LDO.
Figure 9 shows how this circuit can be translated into a
PCB layout.
Figure 8: Recommended application circuit schematic
Label
U1
J1
C
IN
Part Number
ILC7081AIM5-30
69190-405
GRM40 Y5V 105Z16
Manufacturer
Impala Linear
Berg
muRata
Description
100mA RF LDO
Connector, four position header
Ceramic capacitor, 1μF, 16V, SMT
(size 0805)
Ceramic Capacitor, 0.01μF, 16V,
SMT (size 0603)
Ceramic Capacitor, 4.7μF, 16V, SMT
(size 1206)
C
NOISE
ECU-V1H103KBV
Panasonic
C
OUT
GRM42-
6X5R475K10
muRata
Evaluation Board Parts List For Printed Circuit Board Shown Above
1.
2.
3.
4.
1.
2.
3.
4.
Grounding Recommendations
Layout Considerations
Figure 9: Recommended application circuit layout
(not drawn to scale).
Note: ground plane is bottom layer
of PCB and connects to top layer ground connections
through vias
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