
MSCAN Controller
Programmer’s Model of Control Registers
68HC(9)12DG128 Rev 1.0
MOTOROLA
MSCAN Controller
323
37-mscan12
WARNING:
To ensure data integrity, no registers of the transmit buffers should be written
to while the associated TXE flag is cleared
.
NOTE:
The CTFLG register is held in the reset state if the SFTRES bit in
CMCR0 is set.
msCAN12 Transmitter Control Register (CTCR)
ABTRQ2 – ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that a scheduled message
buffer (TXEx = 0) shall be aborted. The msCAN12 grants the request
if the message has not already started transmission or if the
transmission is not successful (lost arbitration or error). When a
message is aborted, the associated TXE and the Abort Acknowledge
flag (ABTAK, see
msCAN12 Transmitter Flag Register (CTFLG)
) are
set and an TXE interrupt is generated if enabled. The CPU cannot
reset ABTRQx. ABTRQx is cleared implicitly whenever the
associated TXE flag is set.
0 = No abort request.
1 = Abort request pending.
NOTE:
The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interruptis generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event results in a transmitter empty interrupt.
NOTE:
The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Bit 7
0
6
5
4
3
0
2
1
Bit 0
CTCR
$0107
RESET
R
W
ABTRQ2
ABTRQ1
ABTRQ0
TXEIE2
TXEIE1
TXEIE0
0
0
0
0
0
0
0
0