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參數(shù)資料
| 型號(hào)： | 68HC05M68HC |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁數(shù)： | 62/130頁 |
| 文件大?。?/td> | 1541K |
| 代理商： | 68HC05M68HC |
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Serial Input/Output Port (SIOP)
Advance Information
MC68HC705P6A
—
Rev. 2.0
62
Serial Input/Output Port (SIOP)
MOTOROLA
7.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
7.4.1 SIOP Control Register (SCR)
This register is located at address $000A and contains two bits.
Figure
7-3
shows the position of each bit in the register and indicates the value
of each bit after reset.
SPE
—
Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP
control register while a transmission is in progress will cause the SPIF
and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written
once to enable the SIOP and then not written to until the SIOP is to
be disabled. Clearing the SPE bit while a transmission is in progress
Address:
$000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
SPE
0
MSTR
0
0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
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