參數(shù)資料
型號: 68HC05K0
廠商: Motorola, Inc.
英文描述: 8-Bit Microcontroller Units (MCU).(8位微控制器)
中文描述: 8位微控制器單元(MCU)。(8位微控制器)
文件頁數(shù): 10/12頁
文件大?。?/td> 111K
代理商: 68HC05K0
MOTOROLA
10
AN463/D
0153 **************************************************************
0154 * THE DECODE ROUTINE USES TWO ARRAYS. IT COMPARES THE KEY *
0155 * VALUE WITH THE ARRAY KEYDAT AND WHEN A MATCH IS FOUND THE *
0156 * CORRESPONDING ELEMENT IN THE ARRAY TVDAT BECOMES THE *
0157 * TRANSMITTED CODE. *
0158 **************************************************************
0159
0160 0287 ae 18 decode ldx #$18 ; data array offset to zero
0161 0289 d6 03 02 nxtel lda keydat,x ; look at each element of array
0162 028c b1 e1 cmp keyst2 ; compare with key read
0163 028e 27 03 beq match ; decode if match
0164 0290 5a decx ; else try next element
0165 0291 26 f6 bne nxtel ; norm if no match found
0166 0293 d6 03 1a match lda tvdat,x ; get key code
0167 0296 b7 e1 sta keyst2 ; store code to transmit
0168 0298 81 rts
0169
0170 **************************************************************
0171 * THE TRANSMISSION PROTOCOL REQUIRES A PRE-BIT, A PRE-BIT *
0172 * PAUSE, A START BIT AND NINE DATA BITS, WHERE THE PRE-BIT *
0173 * AND THE START BIT ARE LOGIC '1'. *
0174 **************************************************************
0175
0176 0299 10 e3 trnmit bset 0,dflag ; initialise for first bit
0177 029b ad 32 bsr send1 ; send pre-bit
0178 029d cd 02 fc jsr datwt ; pre-bit pause
0179 02a0 cd 02 fc jsr datwt ; equalling four half data periods
0180 02a3 cd 02 fc jsr datwt ;
0181 02a6 cd 02 fc jsr datwt ;
0182 02a9 ad 24 bsr send1 ; send start bit
0183 02ab ae 08 ldx #$08 ; transmit 8 data bits
0184 02ad 34 e2 nxtbit lsr keyst3 ; get next bit
0185 02af 25 04 bcs data1 ; send 1 if carry set
0186 02b1 ad 28 bsr send0 ; send 0 if carry clear
0187 02b3 20 02 bra bitsnt
0188 02b5 ad 18 data1 bsr send1
0189 02b7 5a bitsnt decx ; countdown bits sent
0190 02b8 26 f3 bne nxtbit ; send next bit if count not zero
0191 02ba 03 e3 04 brclr 1,dflag,send00 ; if flag set
0192 02bd ad 10 bsr send1 ; send 1 as nineth bit
0193 02bf 20 02 bra endend ;
0194 02c1 ad 18 send00 bsr send0 ; else send 0
0195 02c3 ae 18 endend ldx #$18
0196 02c5 ad 35 loopw bsr datwt ; delay between successive
0197 02c7 ad 33 bsr datwt ; transmissions
0198 02c9 ad 31 bsr datwt
0199 02cb 5a decx
0200 02cc 26 f7 bne loopw
0201 02ce 81 rts
0202
0203
0204 **************************************************************
0205 * TO TRANSMIT A LOGIC '1' A 32kHz PULSE TRAIN FOR 512us IS *
0206 * FOLLOWED BY A 512us PAUSE. *
0207 **************************************************************
0208
0209 02cf 01 e3 04 send1 brclr 0,dflag,last0 ; check if last bit was zero
0210 02d2 a6 10 lda #$10 ; burst if last bit was 1
0211 02d4 ad 15 bsr burst ; 32kHz pulse for 512us
0212 02d6 ad 24 last0 bsr datwt ; wait 512us
0213 02d8 10 e3 bset 0,dflag ; set flag as 1 sent
0214 02da 81 rts
0215
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