
MC68HC05B6
MOTOROLA
vii
INDEX
MC68HC05B8
B–1
block diagram
B–2
memory map
B–3
MC68HC705B16
E–1
block diagram
E–2
memory map
E–3
MC68HC705B16N
F–1
block diagram
F–2
memory map
F–3
MC68HC705B32
H–3
block diagram
H–4
memory map
H–5
MC68HC705B5
C–1
block diagram
C–2
memory map
C–3
mechanical dimensions
12–4
,
12–5
,
12–6
memory map
MC68HC05B16
D–5
MC68HC05B32
G–3
MC68HC05B4
A–3
MC68HC05B6
3–2
MC68HC05B8
B–3
MC68HC705B16
E–3
MC68HC705B16N
F–3
MC68HC705B32
H–5
MC68HC705B5
C–3
Miscellaneous register
INTE
3–9
9–9
INTP, INTN
3–9
,
9–9
POR
3–9
,
9–2
SFA
3–10
,
7–3
SFB
3–10
,
7–3
SM
2–9
,
3–10
,
7–3
WDOG
3–10
,
9–4
modes of operation
jump to any address
2–4
low power modes
2–6
single chip mode
2–1
N
NF – Noise error flag
6–17
nonmaskable software interrupt
9–6
O
OCF1 – Output compare flag 2
5–6
OCF2 – Output compare flag 2
5–7
OCIE – Output compares interrupt enable
5–4
OLV1 – Output level 1
5–5
OLV2 – Output level 2
5–5
Options register
SEC
H–12
options register
EE1P
H–12
EPP
C–7
PBPD
C–8
PCPD
C–8
RTIM
C–7
RWAT
C–7
WWAT
C–7
OPTR – options register
3–6
,
C–7
EE1P – EEPROM protection bit
3–7
SEC – Security bit
3–7
OR – Overrun error flag
6–17
oscillator connections
2–12
,
D–4
Output compare registers
OCR1
5–9
OCR2
5–10
P
parallel bootstrap
E–13
,
E–19
,
F–13
,
H–16
PBPD – Port B pull-down
E–8
,
F–8
PBPD – Port B pull-down resistors
C–8
PCPD – Port C pull-down
E–8
F–9
PCPD – Port C pull-down resistors
C–8
pin configurations
12–1
pins
IRQ
2–10
OSC1, OSC2
2–11
PA0–PA7, PB0–PB7, PC0–PC7
2–13
PD0/AN0–PD7/AN7
2–13
PLMA, PLMB
2–13
RDI, TDO
2–13
RESET
2–10
9–3
SCLK
2–13
TCAP1
2–10
TCAP2
2–11
TCMP1, TCMP2
2–11
VDD, VSS
2–10
VPP1
2–13
VRH, VRL
2–13
PLCC
12–1
PLM
5–11
block diagram
clock selection
7–4
PLMA, PLMB
7–2
POR – Power-on reset bit
3–9
,
9–2
port registers
PORTA, PORTB
4–4
PORTC
4–4
PORTD
4–5
PORTD – Port D data register
8–3
ports
A and B
4–2
C
4–3
D
4–3
power-on reset
9–2
programmable timer
block diagram
5–2
Pulse
5–11
pulse length modulation
5–11
registers
PLMA, PLMB
5–11
TPG