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參數(shù)資料
| 型號(hào)： | 5V60014DVGI8 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO8 |
| 封裝： | 3 MM, ROHS COMPLIANT, MSOP-8 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | 5V60014DVGI8 |
IDT5V60014
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
IDT LOW PHASE NOISE ZERO DELAY BUFFER
2
IDT5V60014
REV D 040609
Pin Assignment
Pin Descriptions
External Components
The IDT5V60014 requires a minimum number of external
components for proper operation.
A decoupling capacitor of 0.01F must be connected
between VDD and GND on each side of the chip (between
pins 2 and 3, and between pins 6 and 5). They must be
connected close to the device to minimize lead inductance.
No external power supply filtering is required for this device.
A 33
terminating resistor can be used next to each output
pin.
CLK2
ICLK
VDD
GND
VDD
CLK1
NC
GND
1
5
8
4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Reference clock input.
2
VDD
Power
Connect to +3.3 V.
3
GND
Power
Connect to ground.
4
CLK2
Output
Clock output.
5
GND
Power
Connect to ground.
6
VDD
Power
Connect to +3.3 V.
7
CLK1
Output
Clock output.
8
NC
-
No connect.
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