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參數(shù)資料
| 型號： | 5962R9566901VCC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 取樣保持放大器 |
| 英文描述： | SAMPLE AND HOLD AMPLIFIER, CDIP14 |
| 封裝： | METAL SEALED, SIDE BRAZED, CERAMIC, DIP-14 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 257K |
| 代理商： | 5962R9566901VCC |
7
HS-2420RH
Offset and Gain Adjustment
Offset Adjustment
The offset voltage of the HS-2420RH may be adjusted using
a 100k
trim pot, as shown in Figure 15. The recommended
adjustment procedure is:
1. Apply 0V to the sample-and-hold input, and a square
wave to the S/H control.
2. Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain
error at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a -10V
output.
5. Measure the output hold voltage (V-10 NOMINAL). Adjust
the trim pot for an output hold voltage of:
V-10 NOMINAL
()
10V
–
()
+
2
------------------------------------------------------------------------
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