參數(shù)資料
型號： 5962L005366VYC
元件分類： SRAM
英文描述： 512K X 8 STANDARD SRAM, 20 ns, CDFP36
封裝： CERAMIC, DFP-36
文件頁數(shù)： 13/16頁
文件大小： 138K
代理商： 5962L005366VYC
6
{
}
VLOAD + 500mV
VLOAD - 500mV
VLOAD
VH - 500mV
VL + 500mV
Active to High Z Levels
High Z to Active Levels
Figure 3. 5-Volt SRAM Loading
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
-55
°C to +125°C for (C) screening and -40oC to +125oC for (W) screening (V
DD = 5.0V + 10%)
Notes: * Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3).
3. The ET (chip enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters.
4. The EF (chip enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters.
SYMBOL
PARAMETER
MIN
MAX
UNIT
tAVAV
1
Read cycle time
20
ns
tAVQV
Read access time
20
ns
tAXQX
Output hold time
3
ns
tGLQX
G-controlled Output Enable time
0
ns
tGLQV
G-controlled Output Enable time (Read Cycle 3)
10
ns
tGHQZ
2
G-controlled output three-state time
10
ns
tETQX
3
E-controlled Output Enable time
3
ns
tETQV
3
E-controlled access time
20
ns
tEFQZ
1,2,4
E-controlled output three-state time
10
ns
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