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參數(shù)資料
| 型號(hào)： | 5962L005365VYA |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| 封裝： | CERAMIC, DFP-36 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 138K |
| 代理商： | 5962L005365VYA |
2
PIN NAMES
DEVICE OPERATION
The UT9Q512E has three control inputs called Chip Enable (E),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). E controls
device selection, active, and standby modes. Asserting E enables
the device, causes IDD to rise to its active value, and decodes the
19 address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min) and E less than VIL
(max) defines a read cycle. Read access time is measured from
the latter of Chip Enable, Output Enable, or valid address to
valid data output.
SRAM Read Cycle 1, the Address Access in figure 4a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 4b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 4c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0)
Address
DQ(7:0)
Data Input/Output
E
Chip Enable
W
Write Enable
G
Output Enable
VDD
Power
VSS
Ground
136
235
334
433
532
631
730
829
928
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
Figure 2. UT9Q512E 20ns SRAM Pinout (36)
NC
A18
A17
A16
A15
G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
E
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W
A5
A6
A7
A8
A9
G
W
E
I/O Mode
Mode
X1
X
1
3-state
Standby
X
0
Data in
Write
1
0
3-state
Read2
0
1
0
Data out
Read
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