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參數(shù)資料
| 型號： | 5962F9683201VCX |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | DUAL OP-AMP, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 44K |
| 代理商： | 5962F9683201VCX |
2
Application Information
Optimum Feedback Resistor
Although a current feedback amplier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplier’s unique relationship between bandwidth and RF.
All current feedback ampliers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplier’s bandwidth is
inversely proportional to RF. The HS-1245RH design is
optimized for a 560
RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For good channel-to-
channel gain matching, it is recommended that all resistors
(termination as well as gain setting) be
±1% tolerance or better.
Note that a series input resistor, on +IN, is required for a gain of
+1, to reduce gain peaking and increase stability.
Non-Inverting Input Source Impedance
For best operation, the D.C. source impedance looking out of
the non-inverting input should be
≥50. This is especially
important in inverting gain congurations where the non-
inverting input would normally be connected directly to GND.
Optional GND Pin for TTL Compatibility
The HS-1245RH derives an internal GND reference for the
digital circuitry as long as the power supplies are
symmetrical about GND. The GND reference is used to
ensure the TTL compatibility of the DISABLE inputs. With
symmetrical supplies the GND pin (Pin 12) may be oated,
or connected directly to GND. If asymmetrical supplies (e.g.
+10V, 0V) are utilized, and TTL compatibility is desired, the
GND pin must be connected to GND.
PC Board Layout
The frequency response of this amplier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
F) tantalum in parallel with a small value
(0.1
F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to -IN, and connections to -IN should be
kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental ne tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth of 290MHz (for AV = +1). By decreasing RS as
CLincreases (as illustrated in the curves), the maximum
bandwidth is obtained without sacrificing stability. Even so,
bandwidth does decrease as you move to the right along
the curve. For example, at AV = +1, RS = 62, CL = 40pF,
the overall bandwidth is limited to 180MHz, and bandwidth
drops to 70MHz at AV = +1, RS = 8, CL = 400pF.
GAIN
(ACL)RF ()
BANDWIDTH
(MHz)
-1
510
230
+1
560 (+
RS = 560)
290
+2
560
530
0
100
200
300
400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
SERIES
OUTPUT
RESIST
ANCE
(
)
AV = +1
AV = +2
150
250
350
50
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
HS-1245RH
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